As advances in processing technology allow for an increasing number of devices to be fabricated on a single integrated circuit (IC), the surface area or size of each individual device on the IC is scaled down or reduced. Conductive lines or interconnects that electrically couple such individual devices, are also scaled. However, the same scaling factor applied to line width and line to line spacing is not generally applied to interconnect line thickness due to the need to maintain minimum current carrying capacity. Thus, interconnect lines are often thicker than that which the scaling factor employed for the line width would predict.
Adjacent interconnect lines form a capacitor where the plate area of each plate of the capacitor formed is the product of the length of the line and its thickness, over that length. The capacitance of such a capacitor is directly proportional to area of the capacitor plates and the dielectric constant of the dielectric material disposed between the plates, and inversely proportional to the distance between the capacitor plates (line-line spacing). Thus, as IC's are scaled down in size the line to line spacing decrease and the increased number of lines that are needed to interconnect the increased number of devices, results in an increase in the line to line capacitance. In addition to this line to line capacitance, the capacitance between interconnects of adjacent levels, often referred to as cross-talk, is also a factor in an IC's total interconnect capacitance. In some high speed circuits, this interconnect capacitance can be the limiting factor in the speed at which the IC can function. Thus it would be desirable to be able to reduce this total interconnect capacitance.
A significant factor in the value of interconnect capacitance is the dielectric constant of the materials that surround interconnect lines, as capacitance is directly proportional to such material's dielectric constant. For example, where silicon nitride, with a dielectric constant of about 7.0, is used as such a material, the resulting capacitance is higher than if silicon dioxide, with a dielectric constant of about 3.9, were employed. However, as silicon oxide is currently the most commonly used material, reduced interconnect capacitance is dependent on new, lower dielectric constant materials. However, it has been found that use of such low dielectric constant (low-K) materials is often problematic.
Thus it would be advantageous to provide improved methods for fabricating advanced IC's that reduce or eliminate this increase in interconnect capacitance as IC's are scaled down in size. It would be desirable if these improved methods provided for forming interconnect lines with low line to line capacitance within a layer of interconnect lines. In addition, it would be desirable if the methods also served to reduce cross-talk between interconnect lines of adjacent layers of such lines. It would also be desirable if this processing method and flow was readily integratable into a standard semiconductor process flow, thus avoiding increased costs and yield losses due to increased process complexity. In this manner, smaller, faster, more complex, and more densely packed integrated circuits such as DRAMs and the like are provided.